As is known, in a typical programmable logic array executed in CMOS technology, the output lines of the input register enter vertically a so-called AND plane, the output lines of the AND plane enter horizontally a so-called OR plane, and the outputs of the OR plane exit vertically toward an output register. The horizontal lines of the AND plane are formed by transistors arranged in series and, where required by the combinatorial function, the transistors are controlled by the vertical lines so as to form an AND function. The horizontal output lines of the AND plane are connected to the supply voltage. In the OR plane, the vertical lines are the ones connected to the supply voltage, and the transistors arranged at the crossing points are controlled by the horizontal lines. The lines which enter and exit the AND plane are typically present in a normal version and in a complemented version in order to be able to obtain any required product term. A two-phase clock alternatively enables the input of the signals to the AND plane and the output of the signals from the OR plane.